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2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
2Mb ZBT(R) SRAM
FEATURES
* * * * * * * * * * * * * * * * * * * High frequency and 100 percent bus utilization Fast cycle times: 10ns and 12ns Single +3.3V 5% power supply Advanced control logic for minimum control signal interface Individual BYTE WRITE controls may be tied LOW Single R/W# (read/write) control pin CKE# pin to enable clock and suspend operations Three chip enables for simple depth expansion Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed, fully coherent WRITE Internally self-timed, registered outputs eliminate the need to control OE# SNOOZE MODE for reduced-power standby Common data inputs and data outputs Linear or Interleaved Burst Modes Burst feature (optional) 100-pin TQFP package 165-pin FBGA package Pin/function compatibility with 4Mb, 8Mb, and 16Mb ZBT SRAM Automatic power-down
MT55L128L18F1, MT55L64L32F1, MT55L64L36F1
3.3V VDD, 3.3V I/O
100-Pin TQFP**
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
* Timing (Access/Cycle/MHz) 7.5ns/10ns/100 MHz 9ns/12ns/83 MHz * Configurations 128K x 18 64K x 32 64K x 36 * Package 100-pin TQFP 165-pin FBGA * Temperature Commercial (0C to +70C)
Part Number Example:
MARKING*
-10 -12 **JEDEC-standard MS-026 BHA (LQFP). MT55L128L18F1 MT55L64L32F1 MT55L64L36F1
GENERAL DESCRIPTION
The Micron(R) Zero Bus TurnaroundTM (ZBT(R)) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The MT55L128L18F1 and MT55L64L32/36F1 SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization, eliminating turnaround cycles for READ to WRITE, or WRITE to READ, transitions. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables
T F
None
MT55L128L18F1T-10
* A Part Marking Guide for the FBGA devices can be found on Micron's web site--http://www.micron.com/support/index.html.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM 128K x 18
17 SA0, SA1, SA MODE CLK CKE# K CE ADDRESS REGISTER 17 SA1 D1 SA0 D0 ADV/LD# K WRITE ADDRESS REGISTER 15 Q1 SA1' SA0' Q0 17 17 O U T P U T B U F F E R S E 17
BURST LOGIC
ADV/LD# BWa# BWb# R/W# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
18
128K x 9 x 2 WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
18
DQs DQPa DQPb
OE# CE# CE2 CE2#
18
READ LOGIC
INPUT E REGISTER
18
FUNCTIONAL BLOCK DIAGRAM 64K x 32/36
16 SA0, SA1, SA MODE CLK CKE# K CE ADV/LD# K WRITE ADDRESS REGISTER ADDRESS REGISTER 16 SA1 D1 SA0 D0 14 Q1 SA1' SA0' Q0 16 16 O U T P U T B U F F E R S E 16
BURST LOGIC
ADV/LD# BWa# BWb# BWc# BWd# R/W# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
36
64K x 8 x 4 (x32) WRITE DRIVERS 64K x 9 x 4 (x36) MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
36
DQs DQPa DQPb DQPc DQPd
36
OE# CE# CE2 CE2#
INPUT E REGISTER
36
READ LOGIC
NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and timing diagrams for detailed information.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION (continued)
for easy depth expansion (CE2, CE2#), cycle start input (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc# and BWd#) and read/write (R/W#). Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The flow-through data-out (Q) is enabled by OE#. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV/LD#). Use of burst mode is optional. It is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address. To allow for continuous, 100 percent use of the data bus, the flow-through ZBT SRAM uses a LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The write data associated with the address is required one cycle later, or on the rising edge of clock cycle two. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; and BWd# controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions. Micron's 2Mb ZBT SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTLcompatible. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. Please refer to Micron's Web site (www.micronsemi.com/datasheets/zbtds.html) for the latest data sheet.
PIN ASSIGNMENT TABLE
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x32 x36 NC DQPc DQc DQc DQc DQc VDDQ VSS NC DQc DQc NC DQc DQc DQb DQc DQc DQb DQc DQc VSS VDDQ DQb DQc DQc DQb DQc DQc VSS VDD VDD VSS DQb DQd DQd DQb DQd DQd VDDQ VSS DQb DQd DQd DQb DQd DQd DQPb DQd DQd NC DQd DQd x18 NC NC NC PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32 x36 VSS VDDQ NC DQd DQd NC DQd DQd NC NC DQPd MODE (LBO#) SA SA SA SA SA1 SA0 DNU DNU VSS VDD DNU DNU SA SA SA SA SA SA NC/SA* PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x32 x36 NC DQPa DQa DQa DQa DQa VDDQ VSS NC DQa DQa NC DQa DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD VSS VSS DQa DQb DQb DQa DQb DQb VDDQ VSS DQa DQb DQb DQa DQb DQb DQPa DQb DQb NC DQb DQb x18 NC NC NC PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 x32 x36 VSS VDDQ DQb DQb DQb DQb NC DQPb SA SA NF* NF* ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# BWc# BWc# BWd# BWd# CE2 CE# SA SA
NC NC SA
NC NC
* Pins 50, 83, and 84 are reserved for address expansion.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
PIN ASSIGNMENT (Top View) 100-Pin TQFP
SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS VSS VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
NC/SA** SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#)
SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQPb* DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VSS VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQPa*
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
x32/x36
NC/SA** SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#)
* NC for x32 version, DQPx for x36 version. ** Pins 50, 83 and 84 are reserved for address expansion.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
NC/DQPc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd*
4
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
PIN DESCRIPTIONS
TQFP (x18) 37 36 32-35, 44-49, 80-82, 99, 100 TQFP (x32/x36) 37 36 32-35, 44-49, 81, 82, 99, 100 SYMBOL SA0 SA1 SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 50, 83, and 84 are reserved as address bits for the higher-density 4Mb, 8Mb, and 16Mb ZBT SRAMs, respectively. SA0 and SA1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDECstandard term for OE#. Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored.
93 94 - -
93 94 95 96
BWa# BWb# BWc# BWd#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86
86
OE# (G#) ADV/LD#
Input
85
85
Input
87
87
CKE#
Input
64
64
ZZ
Input
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
PIN DESCRIPTIONS (continued)
TQFP (x18) 88 TQFP (x32/x36) 88 SYMBOL R/W# TYPE Input DESCRIPTION Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE.
31
31
MODE (LBO#)
Input
(a) 58, 59, 62, 63, 68, 69, 72-74 (b) 8, 9, 12, 13, 18, 19, 22-24
(a) 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 51 80 1 30 n/a
DQa DQb DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd NC
Input/ SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb Output pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK.
74 24
NC/ I/O
No Connect/Data Bits: On the x32 version, these pins are no connect (NC) and can be left floating or connected to GND to minimize thermal impedance. On the x36 version, these bits are DQs. No Connect: These pins can be left floating or connected to GND to minimize thermal impedance.
1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 95, 96 50
NC
50
NC/SA
NC
15, 16, 41, 65, 91 15, 16, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 38, 39, 42, 43 83, 84 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 38, 39, 42, 43 83, 84
VDD VDDQ VSS
Supply Supply Supply
No Connect: NC pin 50 is reserved as an address bit for the higher-density 4Mb ZBT SRAM. This pin can be left floating or connected to GND to minimize thermal impedance. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND.
DNU NF
- -
Do Not Use: These signals may either be unconnected or wired to GND to minimize thermal impedance. No Function: These pins are internally connected to the die and will have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. Pins 83 and 84 are reserved as address bits for the 8Mb and 16Mb ZBT SRAMs.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
6
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
PIN LAYOUT (TOP VIEW) 165-PIN FBGA x18
1 2 3 4 5 6 7 8 9 10 11
1 2 3 4
x32/x36
5 6 7 8 9 10 11
A NC B NC C NC D NC E NC F NC G NC H VSS J DQb K DQb L DQb M DQb N DQPb P NC R MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA NC NC SA SA DNU SA1 DNU SA SA SA NC NC VDDQ VSS NC NC VSS VSS VDDQ NC NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC VDD NC VDD VSS VSS VSS VDD NC NC ZZ DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa SA CE2 NC BWa# CLK R/W# OE# (G#) NC SA NC SA CE# BWb# NC CE2# CKE# ADV/LD# NC SA SA
A
A NC SA CE# BWc# BWb# CE2# CKE# ADV/LD# NC SA NC
A
B
B NC SA CE2 BWd# BWa# CLK R/W# OE# (G#) NC SA NC
B
C
C
NC/DQPc
C NC VDDQ VSS VSS VSS VSS VSS VDDQ NC
NC/DQPb
D
D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
D
E
E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
E
F
F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
F
G
G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
G
H
H VSS VDD NC VDD VSS VSS VSS VDD NC NC ZZ
H
J
J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
J
K
K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
K
L
L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
L
M
M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
M
N
N
NC/DQPd
N NC VDDQ VSS NC NC VSS VSS VDDQ NC
NC/DQPa
P
P NC NC SA SA DNU SA1 DNU SA SA SA NC
P
R
R MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA NC
R
TOP VIEW
TOP VIEW
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. NOTE: Pins 11R, 9A, and 9B are reserved for address expansion; 4Mb, 8Mb, and 16Mb respectively.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS
x18 x32/x36 SYMBOL SA0 SA1 SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 6R 6R 6P 6P 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 8P, 8R, 9P, 9R, 10A, 10B 9R, 10A, 10B 10P, 10R, 11A 10P, 10R 5B 4A - - 5B 5A 4A 4B
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For the x32 and x36 versions, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# controls DQds and DQPd. Parity is only available on the x18 and x36 versions. Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded.
6B
6B
CLK
Input
3A
3A
CE#
Input
6A
6A
CE2#
Input
7A
7A
CKE#
Input
11H
11H
ZZ
Input
7B
7B
R/W#
Input
3B
3B
CE2
Input
(continued on next page)
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
8
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18 8B 8A x32/x36 8B 8A SYMBOL OE#(G#) ADV/LD# TYPE Input DESCRIPTION Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
Input Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ingored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. Input Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating.
1R
1R
MODE (LB0#)
(a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, 10E, 1L, 1M, 2D, 10F, 10G, 11D, 2E, 2F, 2G 11E, 11F, 11G (c) 1D, 1E, 1F, 1G, 2D, 2E, 2F, 2G (d) 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M 11C 1N - - 11N 11C 1C 1N
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated DQas; Output Byte "b" is associated with DQbs. For the x32 and x36 versions, Byte "a" is associated with DQas; Byte "b" is associated with DQbs; Byte "c" is associated with DQcs; Byte "d" is associated with DQds. Input data must meet setup and hold times around the rising edge of CLK.
DQc
DQd
NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD
NC/ I/O
No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd.
2H, 4D, 4E, 4F, 2H, 4D, 4E, 4F, 4G, 4H, 4J, 4G, 4H, 4J, 4K, 4L, 4M, 4K, 4L, 4M, 8D, 8E, 8F, 8D, 8E, 8F, 8G, 8H, 8J, 8G, 8H, 8J, 8K, 8L, 8M 8K, 8L, 8M 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N
Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range.
(continued on next page)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL VSS TYPE Supply Ground: GND. DESCRIPTION 1H, 4C, 4N, 5C, 1H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, 6H, 6J, 6G, 6H, 6J, 6K, 6L, 6M, 6K, 6L, 6M, 7C, 7D, 7E, 7C, 7D, 7E, 7F, 7G, 7H, 7F, 7G, 7H, 7J, 7K, 7L, 7J, 7K, 7L, 7M, 7N, 8C, 8N 7M, 7N, 8C, 8N 5P, 5R, 7P, 7R 5P, 5R, 7P, 7R 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1P, 2C, 2J, 2K, 2L, 2M, 2N, 2P, 2R, 3H, 4B, 5A, 5N, 6N, 9A, 9B, 9H, 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N, 11P, 11R 1A, 1B, 1P, 2C, 2N, 2P, 2R, 3H, 5N, 6N, 9A, 9B, 9H, 10C, 10H, 10N, 11A, 11B, 11P, 11R
DNU NC
- -
Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation.
NOTE: Pins 11R, 9A, and 9B are reserved for address expansion; 4Mb, 8Mb, and 16Mb respectively.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
10
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECOND ADDRESS (INTERNAL) X...X01 X...X00 X...X11 X...X10 THIRD ADDRESS (INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTH ADDRESS (INTERNAL) X...X11 X...X10 X...X01 X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECOND ADDRESS (INTERNAL) X...X01 X...X10 X...X11 X...X00 THIRD ADDRESS (INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTH ADDRESS (INTERNAL) X...X11 X...X00 X...X01 X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)
FUNCTION READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE ABORT/NOP R/W# H L L L L BWa# X L H L H BWb# X H L L H
NOTE: Using R/W# and byte write(s), any one or more bytes may be written.
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)
FUNCTION READ WRITE Byte "a" WRITE Byte "b" WRITE Byte "c" WRITE Byte "d" WRITE All Bytes WRITE ABORT/NOP R/W# H L L L L L L BWa# X L H H H L H BWb# X H L H H L H BWc# X H H L H L H BWd# X H H H L L H
NOTE: Using R/W# and byte write(s), any one or more bytes may be written.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
State Diagram for ZBT SRAM
DS BURST DS DESELECT DS
RE
AD DS
W RI TE S D
WRITE READ
READ
BEGIN READ
BEGIN WRITE
WRITE
READ
BURST
W
BURST BURST READ
E RIT
RE
BURST AD
WRITE
BURST WRITE
BURST
KEY:
COMMAND DS READ WRITE BURST
OPERATION DESELECT New READ New WRITE BURST READ, BURST WRITE or CONTINUE DESELECT
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK).
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
TRUTH TABLE
(Notes 5-10) OPERATION DESELECT CYCLE DESELECT CYCLE DESELECT CYCLE CONTINUE DESELECT CYCLE READ CYCLE (Begin Burst) READ CYCLE (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE CYCLE (Begin Burst) WRITE CYCLE (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE ADDRESS USED None None None None External Next External Next External Next None Next Current None CE# CE2# CE2 ZZ H X X X L X L X L X L X X X X H X X L X L X L X L X X X X X L X H X H X H X H X X X L L L L L L L L L L L L L H ADV/ R/W# BWx OE# CKE# CLK DQ NOTES LD# L X X X L LH High-Z L X X X L LH High-Z L X X X L LH High-Z H X X X L LH High-Z 1 L H X L L LH Q H L H L H L H X X X H X L X L X X X X X X L L H H X X L H H X X X X X X L L L L L L L H X LH Q 1, 11 2 1, 2, 11 3 1, 3, 11 2, 3 1, 2, 3, 11 4
LH High-Z LH High-Z LH LH D D
LH High-Z LH High-Z LH X - High-Z
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first. 2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an application's requirements. 4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#, BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BWa# enables WRITEs to Byte "a" (DQa pins); BWb# enables WRITEs to Byte "b" (DQb pins); BWc# enables WRITEs to Byte "c" (DQc pins); BWd# enables WRITEs to Byte "d" (DQd pins). 7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 8. Wait states are inserted by setting CKE# HIGH. 9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle. 11. The address counter is incremented for all CONTINUE BURST cycles.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS . -0.5V to VDD VIN ........................................... -0.5V to VDDQ + 0.5V Storage Temperature (plastic) ............ -55C to +150C Junction Temperature** ................................... +150C Short Circuit Output Current ........................... 100mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C TA +70C; VDD, VDDQ = +3.3V 0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS DQ pins 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA SYMBOL VIH VIH VIL ILI ILO VOH VOL VDD VDDQ MIN 2.0 2.0 -0.3 -1.0 -1.0 2.4 - 3.135 3.135 MAX VDD + 0.3 VDD + 0.3 0.8 1.0 1.0 - 0.4 3.465 VDD UNITS V V V A A V V V V NOTES 1, 2 1, 2 1, 2 3
1, 4 1, 4 1 1, 5
TQFP CAPACITANCE
DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS TA = 25C; f = 1 MHz VDD = 3.3V SYMBOL CI CO CA CCK TYP 2.7 4 2.5 2.5 MAX 3.5 5 3.5 3.5 UNITS pF pF pF pF NOTES 6 6 6 6
FBGA CAPACITANCE
DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance TA = 25C; f = 1 MHz CONDITIONS SYMBOL CI CO CCK TYP 2.5 4 2.5 MAX 3.5 5 3.5 UNITS pF pF pF NOTES 6, 7 6, 7 6, 7
NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA Power-up: VIH +3.465V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply. 6. This parameter is sampled. 7. Preliminary package data.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(0C TA +70C; VDD, VDDQ = +3.3V 0.165V unless otherwise noted) MAX DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; CKE# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) ZZ VIH SYMBOL IDD TYP 85 -10 225 -12 185 UNITS NOTES mA 1, 2, 3
IDD1
5
12
10
mA
1, 2, 3
CMOS Standby
ISB2
0.5
10
10
mA
2, 3
TTL Standby
ISB3
7
25
25
mA
2, 3
Clock Running
ISB4 ISB2Z
25 0.5
65 10
60 10
mA mA
2, 3 3
Snooze Mode
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. SYMBOL JA JC TYP 40 8 UNITS NOTES C/W C/W 4 4
FBGA THERMAL RESISTANCE
DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Pins (Bottom) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. SYMBOL JA JC JB TYP 40 9 17 UNITS NOTES C/W C/W C/W 4, 5 4, 5 4, 5
NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device is active (not in deselected mode). 3. Typical values are measured at 3.3V, 25C, and 12ns cycle time. 4. This parameter is sampled. 5. Preliminary package data.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0C TA +70C; VDD, VDDQ = +3.3V 0.165V)
DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in NOTE: 1. 2. 3. 4. 5. 6. SYMBOL
tKHKH fKF tKHKL tKLKH tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX tGHQZ tAVKH tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX
-10 MIN MAX 10 100 3.0 3.0 7.5 3.0 3.0 5.0 5.0 0 5.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5
-12 MIN MAX UNITS 12 83 4.0 4.0 9.0 3.0 3.0 5.0 5.0 0 5.0 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES
1 1
2 2, 3, 4, 5 2, 3, 4, 5 6 2, 3, 4, 5 2, 3, 4, 5 7 7 7 7 7 7 7 7
Measured as HIGH above VIH and LOW below VIL. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion on these parameters. This parameter is sampled. Output loading is specified with CL = 5pF as shown in Figure 2. Transition is measured 200mV from steady state voltage. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for turnaround timing. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled. 8. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. 9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
AC TEST CONDITIONS
Input pulse levels ................................... VSS to 3.0V Input rise and fall times .................................. 1.0ns Input timing reference levels .......................... 1.5V Output reference levels ................................... 1.5V Output load ............................. See Figures 1 and 2
Output Load Equivalents
Q Z O= 50 50 VT = 1.5V
Figure 1
+3.3V 317 Q 351 5pF
LOAD DERATING CURVES
The Micron 128K x 18, 64K x 32 and 64K x 36 ZBT SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves.
Figure 2
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tRZZ, only a DESELECT or READ cycle should be given.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current NOTE: 1. This parameter is sampled. CONDITIONS ZZ VIH SYMBOL ISB2Z
tZZ tRZZ tZZI tRZZI
MIN 0 0 0
MAX 10
tKHKH tKHKH tKHKH
UNITS mA ns ns ns ns
NOTES 1 1 1 1
SNOOZE MODE WAVEFORM
CLK
t ZZ t RZZ
ZZ
t ZZI
I
SUPPLY I ISB2Z t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
READ/WRITE TIMING
1 CLK
tEVKH tKHEX tKHKL tKLKH
2
tKHKH
3
4
5
6
7
8
9
10
CKE#
tCVKH tKHCX
CE# ADV/LD# R/W# BWx# ADDRESS A1
tAVKH tKHAX
A2
A3
tKHQV tKHQX1
A4
tKHQX Q(A3) Q(A4) tGHQZ
A5
tGLQV tKHQZ
A6
A7
DQ
D(A1) tDVKH tKHDX
D(A2)
D(A2+1)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
OE# COMMAND
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1)
tGLQX
tKHQX
WRITE D(A5)
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
READ/WRITE TIMING PARAMETERS
-10 SYMBOL tKHKH fKF
tKHKL tKLKH tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX
-12 SYMBOL tGHQZ tAVKH
tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX
-10
-12
MIN MAX MIN MAX UNITS 10 12 ns 100 83 MHz 3.0 3.0 7.5 3.0 3.0 5.0 5.0 0 0 3.0 3.0 5.0 5.0 4.0 4.0 9.0 ns ns ns ns ns ns ns ns
MIN MAX MIN MAX UNITS 5.0 5.0 ns 2.0 2.5 ns 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns ns
NOTE: 1. 2. 3. 4.
For this waveform, ZZ is tied LOW. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
NOP, STALL AND DESELECT CYCLES
1 CLK CKE# CE# ADV/LD# R/W# BWx# ADDRESS DQ COMMAND
WRITE D(A1)
2
3
4
5
6
7
8
9
10
A1
A2 D(A1)
READ Q(A2) STALL
A3 Q(A2)
READ Q(A3)
A4 Q(A3)
WRITE D(A4) STALL
A5
tKHQZ
D(A4)
NOP READ Q(A5)
Q(A5)
tKHQX DESELECT CONTINUE DESELECT
DON'T CARE
UNDEFINED
NOP, STALL AND DESELECT TIMING PARAMETERS
-10 -12 MIN MAX MIN MAX UNITS 3.0 3.0 ns 5.0 5.0 ns
SYMBOL tKHQX tKHQZ
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE# are tied LOW. 3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
165-PIN FBGA
0.85 0.075 0.10 A SEATING PLANE
A
10.00 BALL A11 165X O 0.45 1.00 (TYP) BALL A1 PIN A1 ID 1.20 MAX PIN A1 ID
7.50 0.05
15.00 0.10
14.00
7.00 0.05 1.00 (TYP)
MOLD COMPOUND: EPOXY NOVOLAC 6.50 0.05 5.00 0.05 13.00 0.10 SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: O .33mm
NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
PIN #1 ID 0.15
+0.03 -0.02
0.32
+0.06 -0.10
22.10
+0.10 -0.15
0.65
20.10 0.10 DETAIL A
0.62 14.00 0.10 +0.20 -0.05 GAGE PLANE
1.50 0.10 0.10
16.00
0.25
0.10
+0.10 -0.05
1.00 (TYP) 0.60 0.15 DETAIL A
1.40 0.05
NOTE:
MAX or typical here noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 1. All dimensions in millimeters
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM
REVISION HISTORY
Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/00 CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF CO; TYP 4pF from 6pF; MAX. 5pF from 7pF CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF Removed IT References, REV 7/00, FINAL ..................................................................................................... July/10/00 Added FBGA Part Marking Guide Removed IT from Part Number Example, REV 6/00, FINAL ....................................................................... June/21/00 Added # of datalines to the databus in the Block Diagrams Added Note - "Preliminary Package Data" to FBGA Capacitance and Thermal Resistance Tables Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 5/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_2.p65 - Rev. 8/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.

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